Title :
Efficient architecture for Reed-Solomon decoder
Author :
Lu, Yung-Kuei ; Shieh, Ming-Der
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
Abstract :
An efficient Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (RiBM) algorithm is presented in this paper. Applying the developed control scheme and the simplified boundary cell, the resulting design can significantly reduce the hardware complexity and have a high throughput rate. Compared with the related works, the proposed design has the advantage of area-time complexity. With TSMC 0.18μm process, the simulation results reveal that the developed RS(255,239) decoder can operate up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 12,668.
Keywords :
Reed-Solomon codes; decoding; RS decoder architecture; Reed-Solomon decoder design; TSMC; area-time complexity; gate count; hardware complexity; reformulated inversionless Berlekamp-Massey algorithm; Algorithm design and analysis; Complexity theory; Computer architecture; Decoding; Hardware; Microprocessors; Reed-Solomon codes;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2080-2
DOI :
10.1109/VLSI-DAT.2012.6212603
