Probability based partial triple modular redundancy technique for reconfigurable architectures

This paper represents a design technique for hardening combinational circuits mapped onto any reconfigurable architecture. An effective and simple algorithm for signal probabilities has been used to detect SEU sensitive gates for a given combinational circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these sensitive gates. PTMR is tested against different circuits to prove its efficacy. With a small loss of SEU immunity, the proposed PTMR scheme can greatly reduce the area overhead as compare to TMR technique. PTMR scheme along with reconfiguration feature of FPGAs can result into a very effective SEU mitigation technique