DocumentCode :
2271836
Title :
Fault tolerant and BIST design of a FIFO cell
Author :
Corno, E. ; Prinetto, P. ; Reorda, M. Soma
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear :
1996
fDate :
16-20 Sep 1996
Firstpage :
233
Lastpage :
238
Abstract :
This paper presents a BIST design of a parametrized FIFO component. The component is currently being used in the standard library of Italtel, the main Italian telecom circuit maker. Design choices have been strongly influenced by industrial constraints imposed by the Italtel design flow. To achieve the desired fault coverage level for faults in the memory and in the control logic, traditional BIST schemes had to be combined with more advanced testing techniques. Different parts of the circuits are tested with different strategies and algorithms to account for their different nature: critical parts of the design, such as the FIFO control unit and the BIST controller are tested with on-line test techniques. The final implementation shows that a high fault coverage is attained with an acceptable area overhead and no speed penalty
Keywords :
built-in self test; logic circuits; logic testing; BIST design; FIFO cell; Italtel; fault tolerant; high fault coverage; on-line test; Built-in self-test; Circuit faults; Circuit testing; Communication industry; Fault tolerance; Libraries; Logic testing; Random access memory; Read-write memory; Telecommunication standards;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
Type :
conf
DOI :
10.1109/EURDAC.1996.558210
Filename :
558210
Link To Document :
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