False path exclusion in delay analysis of RTL-based datapath-controller designs

We present an accurate delay estimation algorithm at the register transfer level. We introduce “resource binding” as an important source of false paths in a register transfer level structure. “Path mismatching” between two path segments may create another type of false path when the data path and controller interact. The existence and creation of such paths and their effect in delay analysis are discussed. We also introduce the Propagation Delay Graph (PDG), whose traversal, for delay analysis, is equivalent to the traversal of sensitizable paths in the datapath