Abstract :
Based on 32-bit reduced instruction set computing (RISC) CPU architecture, Andes´s CPU series are called AndesCore which support designers to exploit SoC platform. Three major application classifications that N8, N9, N10 and N12 can be deployed to, are entry level MCU based application, mid range Linux or RTOS application, and high end Linux application, respectively. Each of N8, N9, N10 or N12, namely AndesCore, has configuration flexibility to be manipulated by the designers more than other competitors was improved average performance and power by 24% and 43%, respectively. In order to reduce time to market, Andes supports SoC platform, with name of AndeShape, that can be used to develop whole SoC with helping designers to compose single N8, N9, N10 or N12 CPU core in FPGA; or dual N12 cores in real chip implementation, designer can always easily develop application they like to.
Keywords :
Linux; field programmable gate arrays; microprocessor chips; reduced instruction set computing; system-on-chip; Andes platform; AndesCore; CPU architecture; FPGA; Linux; N10 CPU core; N8 CPU core; N9 CPU core; RTOS; dual N12 cores; entry level MCU based application; field programmable gate arrays; real chip implementation; reduced instruction set computing; system-on-chip; time to market; Computer architecture; Hardware; Linux; Power demand; Program processors; System-on-a-chip; CPU; RISC; SoC;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
