A novel design methodology for hybrid process 3D-IC

Three-dimensional integrated circuit (3D-IC) is considered to be the most promising technology for modern and future electronic devices manufacturing. However, lots of challenges need to be addressed in order to make 3D-IC technically feasible as well as cost effective. One of the major challenges for 3D-IC is electronic design automation (EDA) due to the lack of true 3D EDA tools. In this paper, we propose a novel design methodology which makes current (2D-IC) EDA tools 3D aware. This methodology can be applied to 3D-ICs with the structure of 2 tiers bonded face to face. Since the process node for each tier of the applied 3D-IC can be different, we name it Hybrid Process 3D-IC. Based on the hierarchical design methodology, low power design techniques, flip-chip physical implementation methods, customized cell libraries and scripts are combined together to build up Hybrid Process 3D-IC design methodology. In order to verify the proposed methodology, a real circuit is designed according to it. The detail of the circuit will be described in the following paragraphs.