Title :
Global stacking for analog circuits
Author :
Arsintescu, Bogdan G. ; Spanoche, S.A.
Author_Institution :
Delft Univ. of Technol., Netherlands
Abstract :
A flexible and efficient method for analog circuit partitioning and transistor stacking is presented. The method is based on a novel algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database. An enhanced set of stacks is obtained with respect to placement constraints. Experimental results show the effectiveness of the methods described
Keywords :
MOS analogue integrated circuits; MOSFET; circuit CAD; transistors; analog circuit partitioning; analog specific constraints; global stacking; heuristics; novel algorithm; pattern database; placement constraints; stack generation; transistor stacking; Analog circuits; CMOS analog integrated circuits; Data mining; Merging; Mesh generation; Minimization methods; Mirrors; Parasitic capacitance; Partitioning algorithms; Stacking;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558234
