A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiency

Author

Wu, Ruili ; Li, Yan ; Lopez, Jerry ; Lie, Donald Y C

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

4

Abstract

In this paper, a monolithic 2-stage differential power amplifier (PA) is designed and fabricated in the 0.35 μm IBM 5PAe SiGe BiCMOS technology where the through-wafer-vias (TWVs) are available. A cascode topology is adopted to relieve the voltage stress for the power stage transistors. All components are integrated on-chip for the PA except the input/output baluns. The envelope tracking (ET) technique is applied to this 2-stage PA to enhance the PAE and linearity for high power-to-average-ratio (PAR) Long-Term-Evolution (LTE) signals. The ET-based PA system achieves a linear output power of 20.4 dBm with a gain of 30.5 dB and an overall system PAE of 22%, using an LTE 16QAM 5 MHz signal with ~7.5 dB PAR at 1.85 GHz. Compared to the 2-stage PA operating with fixed voltage supplies, the ET-based PA system improves the linear output power by 3.2 dB and its system PAE by over 10%.

Keywords

BiCMOS integrated circuits; Long Term Evolution; elemental semiconductors; germanium compounds; power amplifiers; quadrature amplitude modulation; silicon compounds; transistors; ET-based PA system; IBM 5PAe BiCMOS technology; LTE 16QAM signal; Long-Term-Evolution; PAE; PAR; SiGe; cascode topology; envelope tracking; envelope tracking technique; frequency 1.85 GHz; frequency 5 MHz; input-output baluns; integrated on-chip; linear efficiency; linear output power; linear power; linearity; monolithic 2-stage differential power amplifier; power stage transistors; power-to-average-ratio; through-wafer-vias; voltage stress; CMOS integrated circuits; Linearity; Modulation; Power amplifiers; Radio frequency; Silicon germanium; WiMAX; Long-Term-Evolution (LTE); Real Time Spectrum Analyzer (RSA); differential cascode PA; envelope tracking (ET); linear output power; monolithic SiGe BiCMOS power amplifier (PA); peak-to-average-power-ratio (PAPR);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

PENDING

Print_ISBN

978-1-4577-2080-2

Type

conf

DOI

10.1109/VLSI-DAT.2012.6212649

Filename

6212649