Title :
A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines
Author :
Ko, Chun-Lin ; Chang, Chieh-Pin ; Kuo, Chien-Nan ; Chang, Da-Chiang ; Juang, Ying-Zong
Abstract :
A V-band low noise amplifier has been demonstrated in 90 nm CMOS. The LNA design was used the low loss microstrip lines for all matching networks. To fulfill the metal density requirement in fabrication, the ground plane needs slots. The direction of the slot pattern affects the line loss over 30% at 60 GHz, according to the analysis and experimental results. By slot filling under the line, the line loss can be improved 10% further. The topology of LNA is 3 stage common-source cascades for low supply voltage limited by process. Using the microstrip lines, the LNA exhibited a low noise figure of 5.6 dB and a gain of 10.8 dB at 60 GHz with only 5.5 mW from a 1.0 V power supply.
Keywords :
CMOS integrated circuits; low noise amplifiers; microstrip lines; 3 stage common-source cascades; CMOS low noise amplifier; LNA design; V-band low noise amplifier; all matching networks; frequency 60 GHz; ground plane; low loss microstrip lines; metal density requirement; power 5.5 mW; slot pattern; voltage 1 V; CMOS integrated circuits; Conductivity; Gain; Low-noise amplifiers; Metals; Microstrip; Noise measurement; CMOS; V-band; low noise amplifier; transmission line;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2080-2
DOI :
10.1109/VLSI-DAT.2012.6212652