Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Author

Huang, Yu-Jen ; Li, Jin-Fu ; Chou, Che-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

4

Abstract

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 512×16 TSV array in which each TSV cell size is 15 × 15μm² is 6.7%.

Keywords

CMOS integrated circuits; built-in self test; crosstalk; system-on-chip; three-dimensional integrated circuits; 2D system-on-chip designs; 3D IC; 3D integration; BIST scheme; CMOS technology; TSV; built-in self-test scheme; coupling capacitance; crosstalk faults; post-bond test techniques; size 90 nm; through silicon via; Built-in self-test; Through-silicon vias; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

PENDING

Print_ISBN

978-1-4577-2080-2

Type

conf

DOI

10.1109/VLSI-DAT.2012.6212658

Filename

6212658