A basic building block approach to CMOS design of analog neuro/fuzzy systems

Outlines a systematic approach to design fuzzy inference systems using analog integrated circuits in standard CMOS VLSI technologies. The proposed circuit building blocks are arranged in a layered neuro/fuzzy architecture composed of 5 layers: fuzzification, T-norm, normalization, consequent, and output. Inference is performed by using Takagi and Sugeno´s (1989) IF-THEN rules, particularly where the rule´s output contains only a constant term-a singleton. A simple CMOS circuit with tunable bell-like transfer characteristics is used for the fuzzification. The inputs to this circuit are voltages while the outputs are currents. Circuit blocks proposed for the remaining layers operate in the current-mode domain. Innovative circuits are proposed for the T-norm and normalization layers. The other two layers use current mirrors and KCL. All the proposed circuits emphasize simplicity at the circuit level-a prerequisite to increasing system level complexity and operation speed. A 3-input, 4-rule controller has been designed for demonstration purposes in a 1.6 μm CMOS single-poly, double-metal technology. We include measurements from prototypes of the membership function block and detailed HSPICE simulations of the whole controller. These results operation speed in the range of 5 MFLIPS (million fuzzy logic inferences per second) with systematic errors below 1%