DocumentCode :
2273481
Title :
Session 1: Co-design — Part I
Author :
Gauthier, Thierry
Author_Institution :
IRISA
fYear :
2011
fDate :
5-6 June 2011
Firstpage :
1
Lastpage :
1
Abstract :
Hardware/Software co-design is one of the challenges of embedded system design, especially ESL enabled system design. Modeling constructs, models of computation, and timing models at the system level need to be developed so that hardware and software can be uniformly modeled, and later partitioned after simulation based profiling. In this session, two papers will be presented, one on data structures for unified modeling, and another on a unified model of computation. The first paper describes a HW/SW codesign template library (CTL). It allows the usage of high level complex data structures for design space exploration by replacing complex data structures with specific library components for either HW or SW. For HW designs, the library provides the opportunity to map data structures to specific memory structures and it contributes to achieve an efficient memory usage. In the second paper, the authors propose a cyber physical system modeling approach based on process networks. The proposed approach supports Kahn process networks, timed dataflow and signal flow graphs as well as their interfacing. A case study is used to illustrate the usefulness of this unified view of models of computation.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic System Level Synthesis Conference (ESLsyn), 2011
Conference_Location :
San Diego, CA, USA
Print_ISBN :
978-1-4577-0634-9
Electronic_ISBN :
978-1-4577-0632-5
Type :
conf
DOI :
10.1109/ESLsyn.2011.5952278
Filename :
5952278
Link To Document :
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