Title :
From design-time concurrency to effective implementation parallelism: The multi-clock reactive case
Author :
Papailiopoulou, V. ; Potop-Butucaru, D. ; Sorel, Y. ; de Simone, R. ; Besnard, L. ; Talpin, J. -P
Abstract :
We have defined a full design flow starting from high-level domain specific languages (Simulink, SCADE, AADL, SysML, MARTE, SystemC) and going all the way to the generation of deterministic concurrent (multi-threaded) executable code for (distributed) simulation or implementation. Based on the theory of weakly endochronous systems, our flow allows the automatic detection of potential parallelism in the functional specification, which is then used to allow the generation of concurrent (multi-thread) code for parallel, possibly distributed implementations.
Keywords :
clocks; concurrency control; hardware description languages; high level synthesis; multi-threading; parallel processing; AADL; MARTE; SCADE; Simulink; SysML; SystemC; design-time concurrency; deterministic concurrent executable code; distributed simulation; full design flow; high-level domain specific language; multiclock reactive case; multithreaded executable code; parallelism; weakly endochronous system; Adders; Algorithm design and analysis; Computer architecture; Instruction sets; Parallel processing; Synchronization; Vegetation; concurrent; distributed; multi-clock synchronous; multi-thread; weak en-dochrony;
Conference_Titel :
Electronic System Level Synthesis Conference (ESLsyn), 2011
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4577-0634-9
Electronic_ISBN :
978-1-4577-0632-5
DOI :
10.1109/ESLsyn.2011.5952287
