Session 5: FPGAs and synthesis — Part II

As in the previous session on the role of FPGA in ESL based methodology as emulation platform, this session brings together two more papers that focus on the problem of synthesis to an FPGA target from high level models. In the first paper, the authors propose several optimizations to a synthesis algorithm that starts from a particular formalism and ends with an RTL description. The formalism used here combines FSM´s to encode overall structure, PSL-like properties to encode behavior within a state, and concepts of variables to make description more compact. The second paper describes a method to increase the computational density of application-specific systems by eliminating soft processors within these systems, and replacing them with synthesizable finite state machines with datapaths.