BDD-based testability estimation of VHDL designs

In this paper we present a method, based on symbolic ATPG techniques, that allows the designer to predict the testability of a control-oriented complex design specified as a set of interacting VHDL modules. Conversely from existing approaches, our method is purely functional, that is, it does not subsume the knowledge of a gate-level implementation of the system being analyzed. Therefore, it allows us to compute testability estimates with a high degree of accuracy for examples on which existing tools fail due to the enormous amount of information they have to handle when considering the structural implementation of the circuit under investigation. Preliminary experimental results demonstrate the effectiveness of the proposed technique