Title :
Model generation of test logic for macrocell based designs
Author :
de la Torre, E. ; Calvo, J. ; Uceda, J.
Author_Institution :
Univ. Politecnica de Madrid, Spain
Abstract :
This paper presents a set of tools for generation, simulation, evaluation and synthesis of VHDL models of test logic for macrocell based embedded microcontroller based systems. The generated models are described at behavioural level so they fit with system descriptions suited for fast simulation. An IEEE 1149.1 boundary scan implementation is used, providing manufacturing test, online test and monitoring capabilities
Keywords :
boundary scan testing; hardware description languages; logic testing; microcontrollers; software prototyping; IEEE 1149.1 boundary scan implementation; VHDL models; macrocell based designs; macrocell based embedded microcontroller based systems; manufacturing test; model generation; monitoring capabilities; online test; simulation; test logic; Circuit testing; Computational modeling; Costs; Hardware; Logic design; Logic testing; Macrocell networks; Microprocessors; Process design; System testing;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558243
