• DocumentCode
    2274394
  • Title

    Internal architecture of Alpha 21164 microprocessor

  • Author

    Bannon, P. ; Keller, J.

  • Author_Institution
    Digital Equipment Corp., Hudson, MA, USA
  • fYear
    1995
  • fDate
    5-9 March 1995
  • Firstpage
    79
  • Lastpage
    87
  • Abstract
    The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world´s fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.
  • Keywords
    computer architecture; microprocessor chips; 1200 MIPS; 600 MFLOPS; ALPHA microprocessor chip; Alpha 21164 microprocessor; bus interface unit; floating point execution pipelines; internal architecture; memory sub-system; memory unit; quad-issue superscalar instruction unit; Bandwidth; CMOS memory circuits; CMOS process; CMOS technology; Electronics packaging; Microprocessor chips; Pins; Pipelines; Power supplies; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compcon '95.'Technologies for the Information Superhighway', Digest of Papers.
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    1063-6390
  • Print_ISBN
    0-8186-7029-0
  • Type

    conf

  • DOI
    10.1109/CMPCON.1995.512368
  • Filename
    512368
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2274394