DocumentCode :
22744
Title :
An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers
Author :
Seung-Yeob Baek ; Jae-Kyum Lee ; Seung-Tak Ryu
Author_Institution :
Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Volume :
60
Issue :
9
fYear :
2013
fDate :
Sept. 2013
Firstpage :
562
Lastpage :
566
Abstract :
A 12-bit 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) was implemented with a modified addition-only digital error correction (ADEC) and a dual-register-based DAC control as speed-enhancement techniques. The proposed speed-enhanced ADEC (SE-ADEC) scheme employs designated capacitors for redundancy-related DAC operation and thus eliminates MUX stages from the DAC control logic. Further speed enhancement is achieved by the dual-register structure that eliminates the entire DAC switching logic. The prototype ADC was fabricated in a 0.35- μm CMOS process utilizing only thick gate transistors with a minimum gate length of 0.5 μm. With a highly linear capacitor DAC design, the prototype ADC achieves 0.38 LSB INL without calibration. The measured spurious-free dynamic range and signal-to-noise and distortion ratio (SNDR) at a low-frequency operation of 250 kS/s are 88 and 68 dB, respectively. At a sample rate of 3 MS/s, the ADC achieves a peak SNDR of 64 dB with a total power dissipation of 1.23 mW under a 2.3-V supply. The FOMNyq is a 368-fJ/conversion-step.
Keywords :
CMOS integrated circuits; capacitors; digital-analogue conversion; shift registers; CMOS process; DAC control logic; DAC switching logic; MUX stages; SE-ADEC scheme; SNDR; analog-to-digital converter; dual-register-based DAC control structure; linear capacitor DAC design; max-SFDR SAR ADC; modified addition-only digital error correction; power 1.23 mW; redundancy-related DAC operation; signal-to-noise and distortion ratio; size 0.35 mum; speed-enhanced ADEC scheme; speed-enhancement techniques; spurious-free dynamic range; successive approximation register; thick gate transistors; voltage 2.3 V; word length -12 bit; Addition-only digital error correction (ADEC); digital error correction; successive approximation register (SAR) ADC;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2013.2268434
Filename :
6553084
Link To Document :
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