Title :
Advanced performance features of the 64-bit PA-8000
Author_Institution :
Lab. of Eng. Syst., Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
The PA-8000 is Hewlett-Packard´s first CPU to implement the new 64-bit PA2.0 architecture. It combines a high clock frequency with a number of advanced microarchitectural features to deliver industry-leading performance on commercial and technical applications while maintaining full compatibility with all previous PA-RISC binaries. Among these advanced features are a fifty-six entry instruction reorder buffer to support out-of-order execution, a branch target address cache, branch history table, support for multiple outstanding cache misses and dual integer load/store, floating point multiply/accumulate, and divide/square root units which allow execution of four instructions per cycle. Together these features will enable the PA-8000 to sustain superscalar operation on a wide variety of workloads.
Keywords :
computer architecture; performance evaluation; scheduling; 64-bit PA-8000; Hewlett-Packard; PA-RISC binaries; PA2.0 architecture; branch history table; branch target address cache; divide/square root units; dual integer load/store; floating point multiply/accumulate; high clock frequency; instruction reorder buffer; microarchitectural features; multiple outstanding cache misses; out-of-order execution; performance features; superscalar operation; Clocks; Frequency; Hardware; History; Microarchitecture; Out of order; Reduced instruction set computing; Scheduling;
Conference_Titel :
Compcon '95.'Technologies for the Information Superhighway', Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-7029-0
DOI :
10.1109/CMPCON.1995.512374
