Flat-top flash annealing™ for advanced CMOS processing

Millisecond annealing (MSA) has proven to be very helpful for continued scaling of CMOS through its applications in forming highly activated ultra-shallow junctions (USJ) and reducing the thermal budget for nickel silicide contact annealing. As device scaling continues, new materials are being introduced, including high-K dielectrics, metal gates, strained channels and even new channel materials, including Ge and III-V semiconductors. This progress also requires ever-decreasing thermal budget, opening up new opportunities for millisecond annealing. Thermal budget constraints arise from the need to limit atomic diffusion and also to prevent undesirable phase transitions, strain relaxation or defect formation. Limits on the maximum process temperature make it desirable to enable process innovations by extending millisecond annealing beyond the traditional regime of <;1 ms anneal duration. This paper explores how such extended heating profiles can be obtained with the flash-assisted RTP™ technology, where rapid wafer preheating is combined with pulsed surface heating that has a flexible dwell time at the peak temperature, giving the unique ability to perform “soak” anneals in a millisecond time scale. This Flat-Top Flash Annealing™ can help with complex process issues, such as optimization of USJ processes, where there are interactions between dopant activation, diffusion and defect annealing, combined with constraints from device integration requirements. The technology also provides highly uniform and repeatable processing at high wafer throughput, which is essential for high volume manufacturing.