Author :
Jung, D.J. ; Hong, Y.K. ; Kim, H.H. ; Park, J.H. ; Kim, H.S. ; Kang, S.K. ; Kim, J.H. ; Ahn, W.S. ; Choi, D.Y. ; Jung, J.Y. ; Jung, W.W. ; Lee, E.S. ; Goh, H.K. ; Kim, S.Y. ; Kang, J.Y. ; Kang, Y.M. ; Joo, S.H. ; Lee, S.Y. ; Jeong, H.S. ; Kim, Kinam
Abstract :
We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.
Keywords :
MIM devices; ferroelectric capacitors; ferroelectric storage; nanoelectronics; random-access storage; cell capacitors; ferroelectric integration; ferroelectric memories; ferroelectric random access memory; metal-insulator-metal capacitors; nanoscale FRAM; process technology; Etching; Ferroelectric films; Ferroelectric materials; MIM capacitors; Metal-insulator structures; Nanoscale devices; Nonvolatile memory; Plasma applications; Plasma devices; Random access memory;
