Title :
The maximal VHDL subset with a cycle-level abstraction
Author :
Barker, W.C. ; Newton, A. Richard
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The maximal VHDL subset with a cycle-level abstraction is defined. This subset requires that the description have three semantic properties: responsiveness modularity and causality, bur full VHDL is neither modular nor causal. Synchronous VHDL is the responsive, modular and causal subset of VHDL. The compiler uses modularity-checking and causality-checking to identify admissible programs
Keywords :
finite state machines; hardware description languages; admissible programs; causality-checking; compiler; cycle-level abstraction; maximal VHDL subset; modularity-checking; responsiveness modularity; semantic properties; Automata; Computational modeling; Guidelines; Proposals; Tellurium;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558245
