DocumentCode
2274856
Title
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries
Author
Imai, Masashi ; Nanya, Takashi
Author_Institution
Res. Center for Adv. Sci. & Technol., Univ. of Tokyo, Tokyo
fYear
2008
fDate
23-27 June 2008
Firstpage
21
Lastpage
26
Abstract
In this paper, we propose a design method for low-power self-timed combinational circuits and latches based on the 1-out-of-4 encoding method. We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded circuits.
Keywords
combinational circuits; logic design; low-power electronics; 1-out-of-4 encoding method; 1-out-of-4 latch circuit; low-power self-timed combinational circuits; standard cell libraries; Combinational circuits; Crosstalk; Delay; Design methodology; Encoding; Energy consumption; Laboratories; Latches; Libraries; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on
Conference_Location
Xian
ISSN
1550-4808
Print_ISBN
978-1-4244-1838-1
Electronic_ISBN
1550-4808
Type
conf
DOI
10.1109/ACSD.2008.4574590
Filename
4574590
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