Title :
TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire ™ Compilation
Author :
Selvidge, C. ; Agarwal, A. ; Dahl, M. ; Babb, J.
Author_Institution :
Virtual Machine Works, Inc., Cambridge, MA
Abstract :
TIERS is a new pipelined routing and scheduling algorithm implemented in a completeVirtualWire TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.
Keywords :
Algorithm design and analysis; Field programmable gate arrays; Logic design; Network topology; Performance analysis; Phase estimation; Routing; Scheduling algorithm; Virtual machining; Wires;
Conference_Titel :
Field-Programmable Gate Arrays, 1995. FPGA '95. Proceedings of the Third International ACM Symposium on
Conference_Location :
Napa Valley, CA, USA
Print_ISBN :
0-7695-2550-4
DOI :
10.1109/FPGA.1995.241941
