Title :
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
Author :
Hamada, Naohiro ; Shiga, Yuuki ; Saito, Hiroshi ; Yoneda, Tomohiro ; Myers, Chris ; Nanya, Takashi
Author_Institution :
Aizu Univ., Aizuwakamatsu
Abstract :
This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.
Keywords :
C language; asynchronous circuits; circuit analysis computing; network synthesis; C language; RTL model; asynchronous circuits; behavioral description; behavioral synthesis method; bundled-data implementation; Asynchronous circuits; Circuit synthesis; Clocks; Control system synthesis; Informatics; Processor scheduling; Resource management; Scheduling algorithm; Signal synthesis; Space exploration;
Conference_Titel :
Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on
Conference_Location :
Xian
Print_ISBN :
978-1-4244-1838-1
Electronic_ISBN :
1550-4808
DOI :
10.1109/ACSD.2008.4574595
