DocumentCode
2275001
Title
Microarchitecture of HaL´s memory management unit
Author
Chang, David Chih-Wei ; Lyon, David ; Chen, Charles ; Peng, Leon ; Massoumi, Mehran ; Hakimi, Matthew ; Iyengar, Satish ; Li, Ellen ; Remedios, Roque
Author_Institution
HaL Comput. Syst., Campbell, CA, USA
fYear
1995
fDate
5-9 March 1995
Firstpage
272
Lastpage
280
Abstract
This paper discusses the architecture and implementation of HaL´s 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.
Keywords
cache storage; storage management; 64-bit memory management unit; HaL´s memory management unit; I/O systems; bus interfaces; data movement controls; memory coherency; memory subsystems; microarchitecture; virtual-to-physical address translations; Control systems; Data structures; Delay; Hardware; Legged locomotion; Memory management; Microarchitecture; Physics computing; Pipelines; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon '95.'Technologies for the Information Superhighway', Digest of Papers.
Conference_Location
San Francisco, CA, USA
ISSN
1063-6390
Print_ISBN
0-8186-7029-0
Type
conf
DOI
10.1109/CMPCON.1995.512396
Filename
512396
Link To Document