• DocumentCode
    2275071
  • Title

    Automatic diagnosis may replace simulation for correcting simple design errors

  • Author

    Wahba, Ayman M. ; Borrione, Dominique

  • Author_Institution
    Lab. TIMA-UJF, Grenoble, France
  • fYear
    1996
  • fDate
    16-20 Sep 1996
  • Firstpage
    476
  • Lastpage
    481
  • Abstract
    An automated tool for diagnosing simple design errors in VHDL description is presented. The tool is tested on benchmark circuits, and the results show that the error is localized precisely, after the application of a small number of specially generated test patterns. This tool is now integrated within the PREVAILTM system, and is being tested on industrial circuits
  • Keywords
    automatic test software; circuit analysis computing; error correction; fault diagnosis; formal specification; formal verification; hardware description languages; logic testing; VHDL description; automatic diagnosis; benchmark circuits; combinational circuits; industrial circuits; sequential circuits; simple design error correction; specially generated test patterns; test pattern generation; Circuit simulation; Circuit testing; Construction industry; Counting circuits; Error correction; Fault diagnosis; Integrated circuit synthesis; Process design; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
  • Conference_Location
    Geneva
  • Print_ISBN
    0-8186-7573-X
  • Type

    conf

  • DOI
    10.1109/EURDAC.1996.558246
  • Filename
    558246
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2275071