DocumentCode :
2275135
Title :
Verification of conditional partial order graphs
Author :
Mokhov, Andrey ; Yakovlev, Alex
Author_Institution :
Microelectron. Syst. Design Group, Newcastle Univ., Newcastle upon Tyne
fYear :
2008
fDate :
23-27 June 2008
Firstpage :
128
Lastpage :
137
Abstract :
The Conditional Partial Order Graph (CPOG) Model introduced recently is a novel technique for specification and synthesis of asynchronous controllers. It combines advantages of both Petri nets and FSM-based approaches and is capable of modelling systems with a high degree of concurrency and multiple choice. The paper extends the basic model of CPOGs to handle dynamic evaluation of internal control signals and introduces behavioural semantics for CPOGs. The extended model has a strong need for verification support, e.g. reachability analysis, deadlock detection etc. and this paper presents SAT-based characterisations for the most important CPOG verification problems.
Keywords :
Petri nets; asynchronous circuits; computability; finite state machines; logic design; logic testing; microcontrollers; CPOG verification; FSM; Petri net; SAT-based characterisation; asynchronous controller specification; asynchronous controller synthesis; behavioural semantics; conditional partial order graph; internal control signal; Automatic control; Central Processing Unit; Circuit synthesis; Concurrent computing; Control system synthesis; Decoding; Logic design; Microelectronics; Petri nets; Signal synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on
Conference_Location :
Xian
ISSN :
1550-4808
Print_ISBN :
978-1-4244-1838-1
Electronic_ISBN :
1550-4808
Type :
conf
DOI :
10.1109/ACSD.2008.4574604
Filename :
4574604
Link To Document :
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