Planar and nanowire Schottky barrier MOSFETs on SOI with NiSi and epitaxial NiSi2 contacts

The scaling of Schottky barrier (SB)-MOSFETs is investigated experimentally and by simulations for devices with minimum gate length as small as 20nm. The results reveal that the scaling of SB-MOSFETs with undoped silicide contacts and thus with fairly large SB has severe limitations. In contrast to normal MOSFETs, the smaller SB transistors provide lower currents due to the increasing overlap of the source/drain potential in the channel. Better scaling behavior can only be achieved for SB-MOSFETs with SB≤0.1eV. Boron and arsenic implantations into silicide (IIS) are used to lower the effective SB height (SBH). With the reduced effective SBH the experimental results demonstrate that the scaling of SB-MOSFETs behaves like conventional MOSFETs. The performance of nanowire devices is significantly improved due to the better electrostatics and the high hole mobilities on the (110) side walls.