Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays

This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.