• DocumentCode
    2275501
  • Title

    A novel MOSFET structure with asymmetric Schottky and P-N junction source/drain on bulk silicon substrate

  • Author

    Xu, Peng ; Hu, Cheng ; Chen, Mei-Gui ; Zhu, Zhiwei ; Zhang, David Wei ; Wu, Dongping

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2012
  • fDate
    14-15 May 2012
  • Firstpage
    238
  • Lastpage
    241
  • Abstract
    An asymmetric Schottky and P-N junction source/drain MOSFET contains a conventional P-N junction and a hybrid junction for the source and drain or vice versa. Owing to the asymmetric source/drain structure, this device could be used in two different situations: Schottky-junction source MOSFETs and Schottky-junction drain MOSFETs. Performances of MOSFETs featuring a gate length of 100 nm with Schottky-junction source, Schottky-junction drain, Schottky-junction source/drain and conventional P-N junction have been obtained via numerical simulation by using Silvaco software package. The Schottky-junction source MOSFET exhibits significantly lower GIDL leakage current compared with the pure Schottky-barrier MOSFETs and slightly lower drive current compared with conventional P-N junction MOSFETs when the Schottky barrier height is set at 0.13 eV. For the Schottky-junction drain MOSFET, its drive current is found to be similar to that of conventional P-N junction MOSFETs and less sensitive to variations of Schottky barrier height compared with pure Schottky-barrier MOSFET.
  • Keywords
    MOSFET; Schottky barriers; elemental semiconductors; leakage currents; numerical analysis; p-n junctions; silicon; GTDL leakage current; MOSFET structure; P-N junction source-drain MOSFET; Schottky barrier height; Schottky junction drain MOSFET; Schottky junction source MOSFET; Si; Silvaco software package; asymmetric Schottky junction source-drain MOSFET; asymmetric source-drain structure; bulk silicon substrate; electron volt energy 0.13 eV; hybrid junction; numerical simulation; Abstracts; Junctions; Logic gates; MOSFET circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Junction Technology (IWJT), 2012 12th International Workshop on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4673-1258-5
  • Electronic_ISBN
    978-1-4673-1256-1
  • Type

    conf

  • DOI
    10.1109/IWJT.2012.6212849
  • Filename
    6212849