A low-latency and power-efficient Viterbi decoder based on dynamic truncation length

Viterbi decoder is a common module in communication system, which has the requirements of low power and low decoding latency. In this paper, based on path merging property, a dynamic truncation length algorithm and memory architecture is proposed to reduce memory access operations of survivor management. The result shows that more than 30% memory access operations can be reduced with almost no degradation of the error correction capability, and the increased hardware costs is very low. Using this architecture and pipelined Add-Compare-Select operation, we can get a low-latency, power efficient Viterbi decoder.