Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays

This paper investigates area-speed trade-offs for Hierarchical FPGA (HFPGA) architectures. Using a set of new CAD tools, we measured the timing performance of HFPGAs and conventional symmetrical FPGAs using data gathered from experiments on a subset of benchmark circuits from the Microelectronics Centre of North Carolina (MCNC). Experiments were also performed to determine the effect of timing optimized placements on routing channel requirements. These experiments demonstrate that HFPGAs can achieve both better area and speed than symmetrical FPGA architectures.