Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance

In this paper, we study the technology mapping problem for sequentail circuits for LUT-based FPGAs. The conventional approach for this problem is based on a technology mapping algorithm for combinational circuits while assuming the positions of the flip-flops are fixed. We propose a new approach in which FFs can be arbitrarily repositioned by retiming. We present an efficient technology mapping algorithm that produces a mapping solution with the minimum clock period for a circuit without loops under the unit dealy model. The algorithm is also extended to the general delay model, in which case it produces a mapping solution with a clock period at most an interconnect or LUT delay away from the minimum one. Note that the algorithm can also be used for circuits with loops by removing some of the FFs to break the loops before the application of the algorithm. The superiority of our approach is further demonstrated experimentally.