Different operational transconductance amplifier topologies for obtaining very small transconductances

Author

Veeravalli, A. ; Sánchez-Sinencio, E. ; Silva-Martinez, J.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

4

fYear

2000

fDate

2000

Firstpage

189

Abstract

A family of CMOS Operational Transconductance Amplifiers (OTA´s) have been designed for very small G_M´s (of the order of nA/V) in the moderate inversion region of operation using several design schemes such as current division, floating gate input stages and bulk driven techniques. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area and signal to noise ratio (SNR). The design has been sent for fabrication in a 1.2 μm n-well CMOS process with a power supply of 2.7 V

Keywords

CMOS analogue integrated circuits; differential amplifiers; integrated circuit design; integrated circuit noise; operational amplifiers; 1.2 micron; 2.7 V; CMOS OTA family; OTA topologies; SNR; active silicon area; bulk driven techniques; current division; floating gate input stages; moderate inversion region; n-well CMOS process; operational transconductance amplifier; performance characteristics; power consumption; signal to noise ratio; Capacitance; Energy consumption; Equations; Frequency; MOSFETs; Operational amplifiers; Signal to noise ratio; Silicon; Topology; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858720

Filename

858720