Jitter-tolerant clock routing in two-phase synchronous systems

Due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. In the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. Appropriate skew or useful skew can serve as a safety margin to guard against clock jitter. In two-phase clocking, the nonoverlapping interval of two-phase clocks provides an additional degree of freedom to improve either the clock tree cost or jitter-tolerance. We construct a two-phase jitter-tolerant useful-skew tree (JT-UST) such that the susceptibility to clock jitter and the clock tree cost is minimized. Following the Deferred-Merge Embedding (DME) framework, we use a simulated annealing approach to explore the routing topologies and embeddings. Experimental results have shown 63% to 100% reduction of jitter-prone sink pairs over previous clock routing methods while having very comparable clock tree costs.