Title :
Transient analysis of a CMOS inverter driving resistive interconnect
Author :
Tang, Kevin T. ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
Abstract :
Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are characterized by the nth power law model. In order to emphasize the nonlinear behavior of a CMOS inverter, the interconnect is modeled as a lumped RC load. The propagation delay of a CMOS inverter is characterized for both a fast ramp and a slow ramp input signal. The waveform of the output voltage based on these analytic equations is quite close to SPICE assuming a fast ramp input signal. The accuracy of the propagation delay model for both fast ramp and slow ramp input signals is within 7% as compared to SPICE simulations
Keywords :
CMOS logic circuits; delay estimation; electric resistance; integrated circuit interconnections; logic gates; network analysis; transient analysis; CMOS inverter; MOS transistors; fast ramp input signal; lumped RC load model; nonlinear behaviour; nth power law model; output voltage; propagation delay model; resistive interconnect driving; resistive-capacitive interconnect; slow ramp input signal; transient analysis; Equations; Impedance; Integrated circuit interconnections; Inverters; MOSFETs; Propagation delay; Semiconductor device modeling; Signal analysis; Transient analysis; Voltage;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858740
