Title :
Synchronous parallel controller synthesis from behavioural multiple-process VHDL description
Author :
Bilinski, Krzysztof ; Mirkowski, Jaroslaw ; Dagless, Erik L.
Author_Institution :
Dept. of Electr. & Electron. Eng., Bristol Univ., UK
Abstract :
A unified framework and associated algorithms for a behavioural synthesis of parallel controllers from a multiple-process VHDL specification is presented. An extension to FSMs, based on Petri nets, is used as an internal representation of an concurrent system during the synthesis. The VHDL simulation cycle implications are explicitly implemented into the Petri net model. This model is next decomposed into a set of well formed subcontrollers and state assignments are generated
Keywords :
Petri nets; distributed control; finite state machines; formal specification; hardware description languages; high level synthesis; Petri nets; VHDL simulation cycle; behavioural multiple-process VHDL description; concurrent system; state assignments; synchronous parallel controller synthesis; well formed subcontrollers; Automatic control; Boolean functions; Clocks; Concurrent computing; Control system synthesis; Fires; Inhibitors; Petri nets; Power system modeling; Testing;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558252
