Measurement and mismatch-modelling of semiconductor devices in BiCMOS technology

Mismatch simulation models are developed for bipolar transistors and MOS transistors manufactured in a 0.8 μm BiCMOS process. Therefore the mismatch variations are measured and simulation parameters are extracted using various techniques. The measurement data and the simulations based on the extracted parameters are compared. The most suitable method uses a direct fit of the parameter variances by non-linear optimisation and predict the mismatch with sufficient accuracy when implemented in to a circuit simulator. Since systematic mismatch can exceed the stochastic mismatch considerably and space is very restricted on an integrated circuit, the influence of asymmetrical metal covering on matching of MOS transistors is also investigated. A significant offset value in the relative drain current mismatch can be found for unequally covered devices