Reliable analysis of settling errors in SC integrators-application to the design of high-speed ΣΔ modulators

This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, both the integration and the sampling phases are considered. Experimental measurements of the settling error power of a 2nd-order ΣΔ modulator are used to validate the model. When compared to previous models, the new one provides more reliable estimations of the defective settling in optimized high-speed ΣΔ modulators. The results in the paper show up to -16 dB difference in the estimation of the in-band error power of a 2-1-1 mb ΣΔM intended for 14 bit@4 M Samples/s