Writing style for architectural synthesis

An encapsulated writing style of Verilog is described together with models for a corresponding scheduler and synthesizer. The method provides a middle ground between synthesis from behavioral specifications, which implies decisions too difficult for architectural synthesis, and synthesis from pure structural specifications, which necessitates providing full details of the controller and netlist. The input writing style is designed to be as concise as possible. This is done by the encapsulation of the functionality of major submodules, and implicit (inferred) control. In this way it is possible to describe complex functional architectures in an economical and transparent manner. This description can be transformed semi-automatically by steps through intermediate styles and eventually to a pure structural specification containing fall details of timing invocations and interconnections to appropriate controllers. At each stage after the first, the writing styles can be fully accessible to native Verilog simulators. The efficiency and economy of this style is demonstrated by a simulation of the well known DLX processor benchmark with full pipeline bypasses