Air cooling limits of 3D stacked logic processor and memory dies

Through-Silicon-Vias (TSVs) enable 3D stack of logic processor and memory dies with significant improvement in latency and energy efficiency of large memory-bound computations. However, additional layers of memory die increase IC package thermal resistance. Thermal management has been identified as a key challenge to achieve high computation power and memory density in the same package. In this paper we present a numerical study on temperature mapping of 3D stacked dies in air-cooled package. We consider DRAM based memory with low power, mid power, and high power logic processors. We study the effect of logic processor power and number of memory dies on the temperature profile. This study provides thermally viable design space of compute-power to memory-size.