Development of a FC/WB stacked die SiP with 100um pitch F2F micro-bump interconnection

Flip chip on chip (FCoC) has emerged recently as a potential solution for system integration, because of its excellent electrical performance, due to the short connection path between two chips. This paper demonstrates the essential groundwork for establishing die stacking option, on wafer and substrate levels, based on a fine pitch, low profile, flip chip on chip package. The chips are interconnected by micro-bumps, with bump pitch of 100um and bump height of 30mum. This paper reports the process feasibility of performing flip chip on chip bonding on wafer and substrate level. It was shown that it is feasible to assemble the FCoC demonstrator with both the assembly process flows. The results also demonstrated good solder joint reliability of up to 1500cycles, based on the JEDEC reliability test conditions.