Title :
Entity overloading for mixed-signal abstraction in VHDL
Author :
Shi, C. -J Richard
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
In this paper we propose to extend VHDL with entity overloading. With a minimal change to existing VHDL, entity overloading provides a strong support for mixed-signal, mixed-level, and mixed-domain abstractions. It is particularly promising in resolving some issues in VHDL-A language design. Furthermore, we illustrate that, entity overloading can be combined with certain modeling rules to achieve polymorphic netlist
Keywords :
hardware description languages; logic CAD; mixed analogue-digital integrated circuits; VHDL; VHDL-A; entity overloading; mixed-domain; mixed-signal abstraction; polymorphic netlist; Analog computers; Circuit synthesis; Cities and towns; Communications technology; Consumer electronics; Digital circuits; Hardware design languages; Object oriented modeling; Signal design; Signal resolution;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558259
