An analog correlator for a WCDMA receiver

A prototype analog correlator structure suitable for a WCDMA-receiver was implemented. The advantages of this correlator are low power consumption (compared to a digital correlator) and small chip area. The target is to use such correlators as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma-delta analog-to-digital converter and a second order sine type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8 to 512 depending on the PN code length. The circuit was implemented in 0.8 μm CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 μm×686 μm and the current drain is approximately 370 μA