Title :
A low power 12Gb/s 1:4 demultiplexer in 0.18μm CMOS
Author :
Pan Min ; Feng Jun ; Dou Jianhua
Author_Institution :
Inst. of RF & OE-ICs, Southeast Univ., Nanjing, China
Abstract :
To reduce the power consumption, a tree-type and half-rate 1:4 demultiplexer is designed by employing all-CMOS logic in whole circuit. The proposed circuit is realized in TSMC 0.18μm CMOS process. The post simulated result shows that the fully integrated 1:4 DEMUX operates well up to 12Gb/s at a supply voltage of 1.8V, and the peak-to-peak value of output voltage swing is 400mV on an external 50 Ohm load. The total power consumption of the DEMUX is 56mW at 12 Gb/s. The overall chip has a size of 0.475×0.475mm2 and the core size is 0.14mm×0.12mm.
Keywords :
CMOS logic circuits; demultiplexing equipment; logic design; low-power electronics; power supply circuits; CMOS process; DEMUX; TSMC; all-CMOS logic; bit rate 12 Gbit/s; half-rate demultiplexer; low power demultiplexer; output voltage swing; peak-to-peak value; power 56 mW; power consumption; resistance 50 ohm; size 0.18 mum; supply voltage; tree-type demultiplexer; voltage 1.8 V; voltage 400 mV; CMOS integrated circuits; CMOS technology; Clocks; Educational institutions; Latches; Logic gates; Power demand;
Conference_Titel :
High Speed Intelligent Communication Forum (HSIC), 2012 4th International
Conference_Location :
Nanjing, Jiangsu
Print_ISBN :
978-1-4673-0678-2
Electronic_ISBN :
978-1-4673-0676-8
DOI :
10.1109/HSIC.2012.6212981
