Title :
An efficient algorithm for 3D interconnect capacitance extraction considering floating conductors
Author :
Cueto, O. ; Charlet, F. ; Farcy, A.
Author_Institution :
Lab d´´Electron. et de Technol. de l´´Inf., CEA, Centre d´´Etudes Nucleaires de Grenoble, France
Abstract :
With the inclusion of floating conductors in integrated circuits, conventional simulation tools exhibit prohibitive calculation times. A new simulation tool, called ICARE, was developed to extract efficiently the 3D capacitance matrix of interconnect structures embedded in a multi-layered dielectric environment. Using the so-called fictitious domain method, it leads to a coupled linear system, with the potential on a regular 3D grid of a simple-shaped domain, including the dielectric media and the charge on a mesh of the conductor surfaces as unknowns. A specific adaptation of this numerical method is introduced, giving the possibility of taking into account the floating conductors in an efficient way. As a result, realistic structures, consisting of one or two conducting lines surrounded by a great number of floating conductors, are simulated.
Keywords :
SPICE; capacitance; digital simulation; integrated circuit interconnections; integrated circuit modelling; 3D interconnect capacitance extraction; ICARE simulation tool; coupled linear system; efficient algorithm; fictitious domain method; floating conductors; integrated circuits; multi-layered dielectric environment; numerical method; Boundary conditions; Circuit simulation; Conductors; Dielectrics; Electric variables; Integrated circuit interconnections; Integrated circuit modeling; Lagrangian functions; Linear systems; Parasitic capacitance;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on
Print_ISBN :
4-89114-027-5
DOI :
10.1109/SISPAD.2002.1034528