Characterization of multi-barrier tunneling diodes and vertical transistors using 2-D device simulation

A novel memory cell which adopts a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction(MTJ) was proposed recently. The device is known to have potential advantages of scalability, high density, high speed, long data retention time, low voltage operation, low power consumption and good endurability. Characterization and optimization of the vertical transistor with MTJ enables the construction of a novel high-density memory with high speed writing and long data retention time. This paper presents a numerical analysis of the tunnel barriers in explaining I-V characteristics of the vertical transistor. We have characterized the vertical transistor with double and triple barriers from the point of view of the central barrier. We have also performed extensive 2-D device simulation for multi barrier tunneling diodes and vertical transistors with various device parameters. Results of the present analysis are expected to provide guidelines for designing the experiments for optimal transistor fabrications.