An instruction-level software simulation approach to resistance evaluation of cryptographic implementations against power analysis attacks

Power analysis attack, one of the most important side-channel cryptanalysis, poses serious threats to the physical security of cryptographic implementations. In order to assess the physical security of cryptographic implementations, especially within design phases, some fundamental supporting tools appear to be highly helpful. Additionally, such tools are also necessary for performing fair comparisons among various power analysis attacks and different countermeasures. Motivated by this, we proposed an instruction-level power consumption software simulation approach, aiming to analyze and assess the resistance of cryptographic implementations against power analysis attack. One prototype system, which is called IMScale, is developed to validate the correctness and feasibility of our approach. Using IMScale, we carried out multiple DPA attacks against an unprotected AES implementation and a masked AES implementation as well. The results of our experiments firmly validate the correctness and feasibility of our instruction-level power consumption software simulation approach, which are also completely consistent with known ones.