DocumentCode :
2278677
Title :
Testing combinational iterative logic arrays for realistic faults
Author :
Gizopoulos, Dimitris ; Nikolos, Dimitris ; Paschalis, Antonis
Author_Institution :
Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
35
Lastpage :
40
Abstract :
In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficient test set of an ILA for more realistic faults
Keywords :
VLSI; cellular arrays; combinational circuits; fault diagnosis; integrated circuit testing; logic arrays; logic testing; C-testability; ILA; cell fault model; combinational iterative logic arrays; efficient test set; linear-testability; n-pattern tests; one-dimensional logic arrays; realistic faults; two-dimensional logic arrays; Delay; Design automation; Informatics; Libraries; Logic arrays; Logic testing; Sequential analysis; Sufficient conditions; Telecommunication computing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
ISSN :
1093-0167
Print_ISBN :
0-8186-7000-2
Type :
conf
DOI :
10.1109/VTEST.1995.512614
Filename :
512614
Link To Document :
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